FIG. 3 is a block diagram showing the microprogram control device of a computer using the conventional successive address designating method described in Electronics Jan. 27, 1981, pp. 107-111. This microprocessor is an eight bit microcomputer. In FIG. 3, reference numeral 1 designates an 8 bit data bus; reference numeral 2 designates an instruction register; and reference numeral 3 designates an address signal line for sending the content of the instruction register 2 to the multiplexer and address decoder 5. Reference numeral 8 designates an eight bit signal line to the microprogram ROM 12. Reference numeral 11 designates a successive address eight bit signal of the microprogram ROM 12 for the next cycle which is outputted from the microprogram ROM 12. Reference numeral 13 designates a forty-three bit control line between the data path section 25 and the microprogram ROM 12. Reference numeral 26 designates a selector signal line for controlling the multiplexer 5.
FIG. 4 shows a timing chart of the operation of the microprogram control device of FIG. 3. In FIG. 4, reference character O designates a system clock; and reference character IF designates an instruction fetch signal for taking in the instruction code to the instruction register 2 from the data bus 1. Reference character IR designates the content of the instruction register 2 such as an operation code taken in from the data bus 1 by the IF. Reference character AD1 designates an address of the microprogram ROM, and this address has an eight bit width. Reference characters S1 to S3 designate the output of the microprogram ROM 12 for controlling the control line 13 of the data path section 25.
The operation of the microprogram control will be described with reference to FIGS. 3 and 4. The timing chart of FIG. 4 is for a case where an instruction (four cycle instruction) is executed by the microprogram control of FIG. 3. Suppose that the instruction code is a provisional instruction such as AAh (the h designates the hexadecimal representation).
In FIG. 4, when the IF signal is "H" an eight bit instruction code is taken into the instruction register 2 from the data bus 1. At the first cycle, the output from the successive address designating signal line 11 which is a portion of the microcode from the microprogram ROM 12 is taken into the multiplexer and address decoder 5 by the signal of the selector signal line 26, which signal is a portion of the same microcode. In this case, the content of the instruction register 2, that is, the eight bit instruction code becomes the address of the microprogram ROM 12 through the multiplexer 5 (AAh in FIG. 4), and it outputs a control signal to the data path section 25 in accordance with the microcode.
At the second cycle, as the address to be inputted to the microprogram ROM 12, the previous cycle eight bit successive address from the microprogram ROM 12 is obtained because the output of the multiplexer 5 is switched to that input in accordance with the selector signal 26. By this method it is possible to obtain a random value as the successive address.
In the successive cycles, the address output in the previous cycle is inputted to the microprogram ROM 12 to produce a successful control operation until the instruction is concluded. In FIG. 4, the address AD1, AAh.fwdarw.A3h.fwdarw.B4h.fwdarw.C5h, can be outputted in turn from the first cycle.
In such a prior art successive address designating system where the bit width of the instruction code falls in the eight bit class, control becomes impossible when the number of combinations of the control patterns (control lines of forty-three bit) for controlling the CPU becomes larger than 256.
Accordingly, in a case where a bit width of the instruction code of a microcontroller or microprocessor is larger than eight bits, for example, sixteen bits, it is quite ineffective to utilize an access method for the microprogram ROM 12 in which the successive address has a sixteen bit width which is similar to the prior art method of FIG. 3.
Furthermore, as the control pattern for controlling the data path section 25 grows to 2.sup.16 kinds of successive addresses that can be outputted, such a system would not be practical. The instruction code in the microcontroller or the microprocessor is often constituted by an instruction type designating bit; such as an operation instruction, a transfer instruction, or a jump instruction; or an addressing mode designating bit. When the instruction code width falls in the sixteen bit class, the instruction type and the addressing mode are used quite often, and an efficient performance by the prior art cannot be realized by utilizing the successive address designating method.